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SDHC10 Card series
Description
Transcend High Capacity SD Card series are specifically designed to meet the High Capacity, High Definition Audio and Video requirement for the latest Digital Cameras, DV Recorders, Mobile Phones, etc,. The new defined Speed Class enables the host to support AV applications to perform real time recording to the SD memory card.
4~16GB High Capacity Secure Digital Card Features
* RoHS compliant product. * Card Lid material: PC (comply with UL94,Flame Class:HB) * Operating Voltage: 2.7 ~ 3.6V * Operating Temperature: -25 ~ 85 C * Durability: 10,000 insertion/removal cycles * Compatible with SD Specification Ver. 3.0 * Mechanical Write Protection Switch * Supports Speed Class Specification up to Class 10
Placement
* Supports Copy Protection for Recorded Media (CPRM) for SD-Audio * Seamless compatibility with SDMI-compliant digital audio devices * Form Factor: 24mm x 32mm x 2.1mm
Front
Back
Pin Definition
Pin No. 1 2 3 4 5 6 7 8 9 Name Type SD Mode Description Name
CS DI VSS VDD SCLK VSS2 DO RSV RSV
Type
I I S S I S O/PP
SPI Mode Description
Chip Select (neg true) Data In Supply voltage ground Supply voltage Clock Supply voltage ground Data Out
CD/DAT I/O/PP3 Card Detect/Data Line [Bit3] CMD VSS1 VDD CLK VSS2 DAT0 DAT1 DAT2 PP S S I S Command/Response Supply voltage ground Supply voltage Clock Supply voltage ground
I/O/PP Data Line [Bit0] I/O/PP Data Line [Bit1] I/O/PP Data Line [Bit2]
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Transcend Information Inc.
SDHC10 Card series
Architecture
4~16GB High Capacity Secure Digital Card
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SDHC10 Card series
Bus Operating Conditions * General
Parameter
Peak voltage on all lines All Inputs Input Leakage Current All Outputs Output Leakage Current -10 -10
4~16GB High Capacity Secure Digital Card
Symbol
Min.
-0.3
Max.
VDD+0.3 10 10
Unit
V A A
Remark
* Power Supply Voltage
Parameter
Supply voltage Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Power up time
Symbol
VDD VOH VOL VIH VIL
Min.
2.7 0.75* VDD
Max.
3.6 0.125* VDD
Unit
V V V V V ms
Remark
IOH=-100uA@VDD Min. IOL=100uA@VDD Min.
0.625* VDD VDD+0.3 VSS-0.3 0.25* VDD 250
From 0v to VDD Min.
* Current Consumption
The current consumption is measured by averaging over 1 second. Before first command: Maximum 15 mA
* Bus Signal Line Load
The total capacitance CL the CLK line of the SD Memory Card bus is the sum of the bus master capacitance CHOST, the bus capacitance CBUS itself and the capacitance CCARD of each card connected to this line: CL = CHOST + CBUS + *CCARD Where N is the number of connected cards.
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* * * * *
During initialization: Maximum 100 mA Operation in Default Mode: Maximum 100 mA Operation in High Speed Mode: Maximum 200 mA Operation with other functions: Maximum 500 mA.
Parameter
Pull-up resistance Bus signal line capacitance
Symbol
RCMD RDAT CL
Min.
10
Max.
100 40
Unit
k pF
Remark
To prevent bus floating 1 card CHOST+CBUS shall not exceed 30 pF
SDHC10 Card series
Single card capacitance Maximum signal line inductance Pull-up resistance inside card (pin1) RDAT3 10 CCARD
4~16GB High Capacity Secure Digital Card
10 16 90 pF nH k fPP 20 MHz May be used for card detection
Note that the total capacitance of CMD and DAT lines will be consist of CHOST, CBUS and one CCARD only because they are connected separately to the SD Memory Card host. Host should consider total bus capacitance for each signal as the sum of CHOST, CBUS, and CCARD, these parameters are defined by per signal. The host can determine CHOST and CBUS so that total bus capacitance is less than the card estimated capacitance load (CL=40 pF). The SD Memory Card guarantees its bus timing when total bus capacitance is less than maximum value of CL (40 pF).
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SDHC10 Card series
* Bus Signal Levels
4~16GB High Capacity Secure Digital Card
As the bus can be supplied with a variable supply voltage, all signal levels are related to the supply voltage.
To meet the requirements of the JEDEC specification JESD8-1A and JESD8-7, the card input and output voltages shall be within the following specified ranges for any VDD of the allowed voltage range:
Parameter
Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage
Symbol
VOH VOL VIH VIL
Min.
0.75* VDD
Max.
0.125* VDD
Unit
V V V V
Remark
IOH = -100 A @VDD min IOL = -100 A @VDD min
0.625* VDD VSS - 0.3
VDD + 0.3 0.25* VDD
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SDHC10 Card series
* Bus Timing
4~16GB High Capacity Secure Digital Card
Parameter
Clock frequency Data Transfer Mode Clock frequency Identification Mode Clock low time Clock high time Clock rise time Clock fall time Inputs CMD, DAT (referenced to CLK) Input set-up time Input hold time
Symbol
fPP fOD tWL tWH tTLH tTHL tISU tIH
6
Min
0 0(1)/100 10 10
Max.
25 400
Unit
MHz KHz ns ns
Remark
CCARD 10 pF, (1 card) CCARD 10 pF, (1 card) CCARD 10 pF, (1 card) CCARD 10 pF, (1 card) CCARD 10 pF, (1 card) CCARD 10 pF, (1 card) CCARD 10 pF, (1 card) CCARD 10 pF, (1 card)
Clock CLK (All values are referred to min (VIH) and max (VIL)
10 10 5 5
ns ns ns ns
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SDHC10 Card series
Outputs CMD, DAT (referenced to CLK) Output Delay time during Data Transfer Mode tODLY 0
4~16GB High Capacity Secure Digital Card
14
ns
CL 40 pF, (1 card)
Output Delay time during Identification Mode tODLY 0 50 ns CL 40 pF, (1 card) (1) 0 Hz means to stop the clock. The given minimum frequency range is for cases were continues clock is required
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SDHC10 Card series
* Bus Timing (High Speed Mode)
4~16GB High Capacity Secure Digital Card
Parameter
Clock frequency Data Transfer Mode Clock low time Clock high time Clock rise time Clock fall time Inputs CMD, DAT (referenced to CLK) Input set-up time Input hold time Outputs CMD, DAT (referenced to CLK)
Symbol
fPP tWL tWH tTLH tTHL tISU tIH
Min
0 7 7
Max.
50
Unit
MHz ns ns
Remark
CCARD 10 pF, (1 card) CCARD 10 pF, (1 card) CCARD 10 pF, (1 card) CCARD 10 pF, (1 card) CCARD 10 pF, (1 card) CCARD 10 pF, (1 card) CCARD 10 pF, (1 card)
Clock CLK (All values are referred to min (VIH) and max (VIL)
3 3 6 2
ns ns ns ns
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SDHC10 Card series
Output Delay time during Data Transfer Mode Output Hold time
1
4~16GB High Capacity Secure Digital Card
tODLY tOH 2.5 40 14 ns ns pF CL 40 pF, (1 card) CL 40 pF, (1 card) (1 card)
Total System capacitance for each line CL 1) In order to satisfy severe timing, host shall drive only one card.
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SDHC10 Card series
Reliability and Durability
Temperature Operation: -25 / 85 C C
4~16GB High Capacity Secure Digital Card
Storage: -40 (168h) / 85 (500h) C C Junction temperature: max. 95 C Moisture and corrosion Operation: 25 / 95% rel. humidity C Storage: 40 / 93% rel. hum./500h C Salt Water Spray: 3% NaCl/35C; 24h acc. MIL STD Method 1009 Durability Bending Torque Drop test UV light exposure X-ray exposure Visual inspection Shape and form WP Switch cycles 10.000 mating cycles; test procedure: tbd. 10N 0.15N.m or +/-2.5 deg 1.5m free fall UV: 254nm, 15Ws/cm according to ISO 7816-1 0.1 Gy of medium-energy radiation (70 keV to 140 keV, cumulative dose per year) to both sides of the card, according to ISO7816-1. No warp page; no mold skin; complete form; no cavities surface smoothness <= -0.1 mm/cm within contour; no cracks; no pollution (fat, oil dust, etc.) minimum 1000 Cycles(@Slide force 0.4N to 5N)
Minimum moving force of WP witch 40gf (Ensures that the WP switch will not slide while it is inserted to the connector.)
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SDHC10 Card series
Register Information
4~16GB High Capacity Secure Digital Card
Within the card interface six registers are defined: OCR, CID, CSD, RCA, DSR and SCR. These can be accessed only by corresponding commands. The OCR, CID, CSD and SCR registers carry the card/content specific information, while the RCA and DSR registers are configuration registers storing actual configuration parameters.
1. OCR register
The 32-bit operation conditions register stores the VDD voltage profile of the card. Additionally, this register includes status information bits. One status bit is set if the card power up procedure has been finished. This register includes another status bit indicating the card capacity status after set power up status bit. The OCR register shall be implemented by the cards. The 32-bit operation conditions register stores the VDD voltage profile of the card. Bit 7 of OCR is newly defined for Dual Voltage Card and set to 0 in default. If a Dual Voltage Card does not receive CMD8, OCR bit 7 in the response indicates 0, and the Dual Voltage Card which received CMD8, sets this bit to 1. Additionally, this register includes 2 more status information bits. Bit 31 - Card power up status bit, this status bit is set if the card power up procedure has been finished. Bit 30 - Card Capacity Status bit, 0 indicates that the card is SDSC. 1 indicates that the card is SDHC or SDXC. The Card Capacity Status bit is valid after the card power up procedure is completed and the card power up status The OCR register shall be implemented by the cards.
OCR Register Definition
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SDHC10 Card series
4~16GB High Capacity Secure Digital Card
1) This bit is valid only when the card power up status bit is set. 2) This bit is set to LOW if the card has not finished the power up routine. 3) Only UHS-I card supports this bit. A voltage range is not supported if the corresponding bit value is set to LOW. As long as the card is busy, the corresponding bit (31) is set to LOW.
2. CID Register
The Card Identification (CID) register is 128 bits wide. It contains the card identification information used during the card identification phase. Every individual flash card shall have a unique identification number. The structure of the CID register is defined in the following paragraphs: Name Manufacturer ID OEM/Application ID Product name Product revision Product serial number reserved Manufacturing date CRC7 checksum not used, always 1 Field MID OID PNM PRV PSN -MDT CRC Width 8 16 40 8 32 4 12 7 1 CID-slice [127:120] [119:104] [103:64] [63:56] [55:24] [23:20] [19:8] [7:1] [0:0]
The CID Fields
* MID
An 8-bit binary number that identifies the card manufacturer. The MID number is controlled, defined, and allocated to a SD Memory Card manufacturer by the SD-3C, LLC. This procedure is established to ensure uniqueness of the CID register.
* OID
A 2-character ASCII string that identifies the card OEM and/or the card contents (when used as a distribution media either on ROM or FLASH cards). The OID number is controlled, defined, and allocated to a SD Memory Card manufacturer by the SD-3C, LLC. This procedure is established to ensure uniqueness of the CID register.
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4~16GB High Capacity Secure Digital Card
Note: SD-3C, LLC licenses companies that wish to manufacture and/or sell SD Memory Cards, including but not limited to flash memory, ROM, OTP, RAM, and SDIO Combo Cards. SD-3C, LLC is a limited liability company established by Matsushita Electric Industrial Co. Ltd., SanDisk Corporation and Toshiba Corporation.
* PNM
The product name is a string, 5 ASCII characters long.
* PRV
The product revision is composed of two Binary Coded Decimal (BCD) digits, four bits each, representing an "n.m" revision number. The "n" is the most significant nibble and "m" is the least significant nibble. As an example, the PRV binary value field for product revision "6.2" will be: 0110 0010b
* PSN
The Serial Number is 32 bits of binary number.
* MDT
The manufacturing date composed of two hexadecimal digits, one is 8 bit representing the year(y) and the other is four bits representing the month(m). The "m" field [11:8] is the month code. 1 = January. The "y" field [19:12] is the year code. 0 = 2000. As an example, the binary value of the Date field for production date "April 2001" will be: 00000001 0100.
* CRC
CRC7 checksum (7 bits).
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3. CSD Register
The CSD Regsiter shows Definition of the CSD for the High Capacity SD Memory Card and Extended Capacity SD Memory Card (CSD Version 2.0). The following sections describe the CSD fields and the relevant data types for the High Capacity SD Memory Card. CSD Version 2.0 is applied to SDHC and SDXC Cards. The field name in parenthesis is set to fixed value and indicates that the host is not necessary to refer these fields. The fixed values enables host,which refers to these fields, to keep compatibility to CSD Version 1.0. The Cell Type field is coded as follows: R = readable, W(1) = writable once, W = multiple writable.
Name CSD structure reserved data read access-time Field CSD_STRUCTURE (TAAC) Width Value 2 6 8 8 8 12 4 1 01b 00 0000b 0Eh 00h Cell Type CSD-slice R R R R [127:126] [125:120] [119:112] [111:104] [103:96] [95:84] [83:80] [79:79] [78:78] [77:77] [76:76] [75:70] [69:48] [47:47] [46:46] [45:39] [38:32] [31:31]
data read access-time in CLK (NSAC) max. data transfer rate card command classes max. read data block length (TRAN_SPEED) CCC (READ_BL_LEN)
32h, 5Ah, 0Bh or 2Bh R
01x110110101b 9 0 0 0 x 00 0000b xxxxxxh 0 1 7Fh 0000000b 0
R R R R R R R R R R R R R
partial blocks for read allowed (READ_BL_PARTIAL) write block misalignment read block misalignment DSR implemented reserved device size reserved erase single block enable erase sector size write protect group size write protect group enable
(WRITE_BLK_MISALIGN) 1 (READ_BLK_MISALIGN) DSR_IMP C_SIZE (ERASE_BLK_EN) (SECTOR_SIZE) (WP_GRP_SIZE) (WP_GRP_ENABLE) 1 1 6 22 1 1 7 7 1
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SDHC10 Card series
reserved write speed factor max. write data block length (R2W_FACTOR) (WRITE_BL_LEN) 2 3 4 1 5 1 1
4~16GB High Capacity Secure Digital Card
00b 010b 9 0 00000b 0 x x x 00b 00b xxxxxxxb 1
R R R R R R R/W(1) R/W(1) R/W R R R/W -
[30:29] [28:26] [25:22] [21:21] [20:16] [15:15] [14:14] [13:13] [12:12] [11:10] [9:8] [7:1] [0:0]
partial blocks for write allowed (WRITE_BL_PARTIAL) reserved File format group copy flag permanent write protection temporary write protection File format reserved CRC not used, always'1' (FILE_FORMAT_GRP) COPY
PERM_WRITE_PROTECT 1 TMP_WRITE_PROTECT (FILE_FORMAT) CRC 1 2 2 7 1
The CSD Register Fields (CSD Version 2.0)
The following sections describe the CSD fields and the relevant data types. If not explicitly defined otherwise, all bit strings are interpreted as binary coded numbers starting with the left bit first.
* CSD_STRUCTURE
Field structures of the CSD register are different depend on the Physical Specification Version and Card Capacity. The CSD_STRUCTURE field in the CSD register indicates its structure version. The following table shows the version number of the related CSD structure.
CSD_STRUCTURE 0 1 2-3
CSD structure version CSD Version 1.0 CSD Version 2.0 reserved
Card Capacity Standard Capacity High Capacity and Extended Capacity
CSD Register Structure
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SDHC10 Card series
* TAAC
4~16GB High Capacity Secure Digital Card
This field is fixed to 0Eh, which indicates 1 ms. The host should not use TAAC, NSAC, and R2W_FACTOR to calculate timeout and should uses fixed timeout values for read and write operations. TAAC bit position code 2:0 time unit 0=1ns, 1=10ns, 2=100ns, 3=1s, 4=10s, 5=100s, 6=1ms, 7=10ms time value 0=reserved, 1=1.0, 2=1.2, 3=1.3, 4=1.5, 5=2.0, 6=2.5, 7=3.0, 8=3.5, 9=4.0, A=4.5, B=5.0, C=5.5, D=6.0, E=7.0, F=8.0 reserved
6:3
7
* NSAC
This field is fixed to 00h. NSAC should not be used to calculate time-out values.
* TRAN_SPEED
The following table defines the maximum data transfer rate per one data line - TRAN_SPEED: TRAN_SPEED bit 2:0 code transfer rate unit 0=100kbit/s, 1=1Mbit/s, 2=10Mbit/s, 3=100Mbit/s, 4... 7=reserved time value 0=reserved, 1=1.0, 2=1.2, 3=1.3, 4=1.5, 5=2.0, 6=2.5, 7=3.0, 8=3.5, 9=4.0, A=4.5, B=5.0, C=5.5, D=6.0, E=7.0, F=8.0 reserved
6:3
7
Maximum Data Transfer Rate Definition
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4~16GB High Capacity Secure Digital Card
Note that for current SD Memory Cards that field must be always 0_0110_010b (032h) which is equal to 25MHz - the mandatory maximum operating frequency of SD Memory Card. In High-Speed mode, that field must be always 0_1011_010b (05Ah) which is equal to 50MHz. And when the timing mode returns to the default by CMD6 or CMD0 command, its value will be 032h.
* CCC
The SD Memory Card command set is divided into subsets (command classes). The card command class register CCC defines which command classes are supported by this card. A value of `1' in a CCC bit means that the corresponding command class is supported. CCC bit 0 1 ...... 11 class 11 Supported card command class class 0 class 1
Supported Card Command Classes
* READ_BL_LEN
This field is fixed to 9h, which indicates READ_BL_LEN=512 Byte.
* READ_BL_PARTIAL
This field is fixed to 0, which indicates partial block read is inhibited and only unit of block access is allowed.
* WRITE_BLK_MISALIGN
This field is fixed to 0, which indicates that write access crossing physical block boundaries is always disabled in SDHC and SDXC Cards.
* READ_BLK_MISALIGN
This field is fixed to 0, which indicates that read access crossing physical block boundaries is always disabled in SDHC and SDXC Cards.
* DSR_IMP
Defines if the configurable driver stage is integrated on the card. If set, a driver stage register (DSR) must be implemented also.
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4~16GB High Capacity Secure Digital Card
DSR_IMP 0 1
DSR type no DSR implemented DSR implemented
DSR Implementation Code Table
* C_SIZE
This field is expanded to 22 bits and can indicate up to 2 TBytes (It is the same as the maximum memory space specified by a 32-bit block address.) This parameter is used to calculate the user data area capacity in the SD memory card (not include the protected area). The user data area capacity is calculated from C_SIZE as follows: memory capacity = (C_SIZE+1) * 512K byte The Minimum user area size of SDHC Card is 4,211,712 sectors (2GB + 8.5MB). The Minimum value of C_SIZE for SDHC in CSD Version 2.0 is 001010h (4112). The maximum user area size of SDHC Card is (32GB - 80MB) The maximum value of C_SIZE for SDHC in CSD Version 2.0 is 00FF5Fh (65375). The Minimum user area size of SDXC Card is 67,108,864 sectors (32GB). The Minimum value of C_SIZE for SDXC in CSD Version 2.0 is 00FFFFh (65535).
* ERASE_BLK_EN
This field is fixed to 1, which means the host can erase one or multiple units of 512 bytes.
* SECTOR_SIZE
This field is fixed to 7Fh, which indicates 64 KBytes. This value is not related to erase operation. SDHC and SDXC Cards indicate memory boundary by AU size and this field should not be used.
* WP_GRP_SIZE
This field is fixed to 00h. SDHC and SDXC Cards do not support write protected groups.
* WP_GRP_ENABLE
This field is fixed to 0. SDHC and SDXC Cards do not support write protected groups.
* R2W_FACTOR
This field is fixed to 2h, which indicates 4 multiples. Write timeout can be calculated by multiplying the read access time
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* WRITE_BL_LEN
4~16GB High Capacity Secure Digital Card
and R2W_FACTOR. However, the host should not use this factor and should use 250 ms for write timeout
This field is fixed to 9h, which indicates WRITE_BL_LEN=512 Byte.
* WRITE_BL_PARTIAL
This field is fixed to 0, which indicates partial block read is inhibited and only unit of block access is allowed.
* FILE_FORMAT_GRP
This field is set to 0. Host should not use this field.
* COPY
Defines whether the contents is original (=0) or has been copied (=1). Setting this bit to 1 indicates that the card content is a copy. The COPY bit is a one time programmable bit except ROM card.
* PERM_WRITE_PROTECT
Permanently protects the whole card content against overwriting or erasing (all write and erase commands for this card are permanently disabled). The default value is `0', i.e. not permanently write protected.
* TMP_WRITE_PROTECT
Temporarily protects the whole card content from being overwritten or erased (all write and erase commands for this card are temporarily disabled). This bit can be set and reset. The default value is `0', i.e. not write protected.
* FILE_FORMAT
This field is set to 0. Host should not use this field.
* CRC
The CRC field carries the check sum for the CSD contents. The checksum has to be recalculated by the host for any CSD modification. The default corresponds to the initial CSD contents. The following table lists the correspondence between the CSD entries and the command classes. A `+' entry indicates that the CSD field affects the commands of the related command class.
4. RCA Register
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4~16GB High Capacity Secure Digital Card
The writable 16-bit relative card address register carries the card address that is published by the card during the card identification. This address is used for the addressed host-card communication after the card identification procedure. The default value of the RCA register is 0x0000. The value0x0000 is reserved to set all cards into the Stand-by State with CMD7.
5. DSR Register (Optional)
The 16-bit driver stage register is described in detail in Chapter 6.5. It can be optionally used to improve the bus performance for extended operating conditions (depending on parameters like bus length, transfer rate or number of cards). The CSD register carries the information about the DSR register usage. The default value of the DSR register is 0x404.
6. SCR Register
In addition to the CSD register there is another configuration register that named - SD CARD Configuration Register (SCR). SCR provides information on SD Memory Card's special features that were configured into the given card. The size of SCR register is 64 bit. This register shall be set in the factory by the SD Memory Card manufacturer. The following table describes the SCR register content. Description SCR Structure SD Memory Card - Spec. Version data_status_after erases CPRM Security Support DAT Bus widths supported Spec. Version 3.00 or higher Extended Security Support Reserved Command Support bits reserved for manufacturer usage CMD_SUPPORT Field SCR_STRUCTURE SD_SPEC DATA_STAT_AFTER_ERASE SD_SECURITY SD_BUS_WIDTHS SD_SPEC3 EX_ SECURITY Width 4 4 1 3 4 1 4 9 14 32 Cell Type R R R R R R R R R R SCR Slic e [63:60] [59:56] [55:55] [54:52] [51:48] [47] [46:43] [42:34] [33:32] [31:0]
The SCR Fields
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SDHC10 Card series
4~16GB High Capacity Secure Digital Card
* SCR_STRUCTURE
Version number of the related SCR structure in the SD Memory Card Physical Layer Specification. SCR_STRUCTURE SCR structure version 0 1-15 SCR version 1.0 reserved SD Physical Layer Specification Version Version 1.01-3.00
SCR Register Structure Version
* SD_SPEC
Describes the SD Memory Card Physical Layer Specification version supported by this card. SD_SPEC 0 1 2 3-15 Physical Layer Specification Version Number Version 1.0-1.01 Version 1.10 Version 2.00 or Version 3.00 (Refer to SD_SPEC3) reserved Physical Layer Specification Version Physical Layer Specification Version Number Version 2.00 Version 3.00
* SD_SPEC3
SD_SPEC 2 2 SD_SPEC3 0 1
The card manufacturer determines SD_SPEC value by conditions indicated below. All conditions shall be satisfied for each version. The other combination of conditions is not allowed. Essential conditions to indicate Version 1.01 Card (SD_SPEC=0 and SD_SPEC3=0) (1)The card does not support CMD6 (2)The card does not support CMD8 (3) User area capacity shall be up to 2GB Essential conditions to indicate Version 1.10 Card (SD_SPEC=1 and SD_SPEC3=0) (1) The card shall support CMD6 (2) The card does not support CMD8 (3) User area capacity shall be up to 2GB
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4~16GB High Capacity Secure Digital Card
Essential conditions to indicate Version 2.00 Card (SD_SPEC=2 and SD_SPEC3=0) (1) The card shall support CMD6 (2) The card shall support CMD8 (3) The card shall support CMD42 (4) User area capacity shall be up to 2GB (SDSC) or 32GB (SDHC) (5) Speed Class shall be supported (SDHC) Essential conditions to indicate Version 3.00 Card (SD_SPEC=2 and SD_SPEC3=1) (1) The card shall support CMD6 (2) The card shall support CMD8 (3) The card shall support CMD42 (4) User area capacity shall be up to 2GB (SDSC) or 32GB (SDHC) User area capacity shall be more than or equal to 32GB and up to 2TB (SDXC) (5) Speed Class shall be supported (SDHC or SDXC) A card supports any of following functions shall satisfy essential conditions of Version 3.00 Card (1) Speed Class supported under the conditions defined in Ver3.00 (2) UHS-I supported card (3) CMD23 supported card Application Notes: When checking SD_SPEC version in SCR, the host shall not forget that higher SD_SPEC version may be specified in future. It is important to keep compatibility for future version.
* DATA_STAT_AFTER_ERASE
Defines the data status after erase, whether it is `0' or `1' (the status is card vendor dependent).
* SD_SECURITY
This field indicates CPRM Security Specification Version for each capacity card. The definition of Protected Area is different in each capacity card. SD_SECURITY 0 1 2 3 4 CPRM Security Version No Security Not Used SDSC Card (Security Version 1.01) SDHC Card (Security Version 2.00) SDXC Card (Security Version 3.xx)
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5-7 Reserved
4~16GB High Capacity Secure Digital Card
CPRM Security Version
The basic rule of setting this field: SDSC Card sets this field to 2 (Version 1.01) SDHC Card sets this field to 3 (Version 2.00). SDXC Card sets this field to 4 (Version 3.xx). Note that it is mandatory for a regular writable SD Memory Card to support Security Protocol. For ROM (Read Only) and OTP (One Time Programmable) types of the SD Memory Card, the security feature is optional.
* SD_BUS_WIDTHS
Describes all the DAT bus widths that are supported by this card. SD_BUS_WIDTHS Bit 0 Bit 1 Bit 2 Bit 3 Supported Bus Widths 1 bit (DAT0) reserved 4 bit (DAT0-3) reserved
SD Memory Card Supported Bus Widths
Since SD Memory Card shall support at least the two bus modes 1bit or 4bit width then any SD Card shall set at least bits 0 and 2 (SD_BUS_WIDTH="0101").
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Mechanical Dimension
4~16GB High Capacity Secure Digital Card
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4~16GB High Capacity Secure Digital Card
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